Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision | |||
|
en:netzer:spi-slave [2015/02/28 19:23] svesch [Physical connection] Added IO table |
en:netzer:spi-slave [2015/11/04 17:19] svesch [Physical connection] Fixed a typo. |
||
|---|---|---|---|
| Line 28: | Line 28: | ||
| | SPI_INT | Output | Netzer pulls this pin low, if internal states has changed. The master MUST check this line inbetween complete transmissions of eight bit. If the line is low the master MUST stop any pending register access immediately with a rising edge on IO1. The interrupt pin is released after a SPI master write to the interrupts flags register. | | | SPI_INT | Output | Netzer pulls this pin low, if internal states has changed. The master MUST check this line inbetween complete transmissions of eight bit. If the line is low the master MUST stop any pending register access immediately with a rising edge on IO1. The interrupt pin is released after a SPI master write to the interrupts flags register. | | ||
| | IO5 | Output | IO5 is used as handshake pin for increasing data throughput. The pin is low during master transmissions. On finished master transmissions the pin is driven high as soon as the Netzer internal SPI module has detected pending data. During the processing of the received byte the line stays high. If processing is finished and possible data is provided by the slave for shifting out the line returns to low. The master is not allowed to start a new transmission during the high state of IO5. | | | IO5 | Output | IO5 is used as handshake pin for increasing data throughput. The pin is low during master transmissions. On finished master transmissions the pin is driven high as soon as the Netzer internal SPI module has detected pending data. During the processing of the received byte the line stays high. If processing is finished and possible data is provided by the slave for shifting out the line returns to low. The master is not allowed to start a new transmission during the high state of IO5. | | ||
| - | | IO1 | Input | IO1 is used for controlling the register access. A falling edge on IO1 starts a new register access. Netzer awaits the very next byte from master after the edge as register address. A rising edge on the pin stops the register access. For easier connection the SPI_CS pin and IO5 can connected together. | | + | | IO1 | Input | IO1 is used for controlling the register access. A falling edge on IO1 starts a new register access. Netzer awaits the very next byte from master after the edge as register address. A rising edge on the pin stops the register access. For easier connection the SPI_CS pin and IO1 can connected together. | |
