eWicht: ETH97J60.h Source File

00001 
00002 
00003 
00019 /*********************************************************************
00020  * Software License Agreement
00021  *
00022  * Copyright (C) 2002-2008 Microchip Technology Inc.  All rights 
00023  * reserved.
00024  *
00025  * Microchip licenses to you the right to use, modify, copy, and 
00026  * distribute: 
00027  * (i)  the Software when embedded on a Microchip microcontroller or 
00028  *      digital signal controller product ("Device") which is 
00029  *      integrated into Licensee's product; or
00030  * (ii) ONLY the Software driver source files ENC28J60.c and 
00031  *      ENC28J60.h ported to a non-Microchip device used in 
00032  *      conjunction with a Microchip ethernet controller for the 
00033  *      sole purpose of interfacing with the ethernet controller. 
00034  *
00035  * You should refer to the license agreement accompanying this 
00036  * Software for additional information regarding your rights and 
00037  * obligations.
00038  *
00039  * THE SOFTWARE AND DOCUMENTATION ARE PROVIDED "AS IS" WITHOUT 
00040  * WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING WITHOUT 
00041  * LIMITATION, ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR A 
00042  * PARTICULAR PURPOSE, TITLE AND NON-INFRINGEMENT. IN NO EVENT SHALL 
00043  * MICROCHIP BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR 
00044  * CONSEQUENTIAL DAMAGES, LOST PROFITS OR LOST DATA, COST OF 
00045  * PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS 
00046  * BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE 
00047  * THEREOF), ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER 
00048  * SIMILAR COSTS, WHETHER ASSERTED ON THE BASIS OF CONTRACT, TORT 
00049  * (INCLUDING NEGLIGENCE), BREACH OF WARRANTY, OR OTHERWISE.
00050  *
00051  *
00052  * Author               Date        Comment
00053  *~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
00054  * Howard Schlunder     06/12/05    Modified for 97J60 (from ENC28J60)
00055  * Howard Schlunder     03/23/06    Updated for Advance Data Sheet
00056  * Howard Schlunder     06/29/06    Changed MACON3_PHDRLEN to MACON3_PHDREN
00057  * Howard Schlunder     09/13/06    Removed a lot of bits for 
00058  *                                  preliminary data sheet, added RXAPDIS
00059  ********************************************************************/
00060 
00061 #ifndef __ETH97J60_H
00062 #define __ETH97J60_H
00063 #include "GenericTypeDefs.h"
00064 
00065 typedef union {
00066     BYTE v[7];
00067     struct {
00068         WORD     ByteCount;
00069         unsigned CollisionCount:4;
00070         unsigned CRCError:1;
00071         unsigned LengthCheckError:1;
00072         unsigned LengthOutOfRange:1;
00073         unsigned Done:1;
00074         unsigned Multicast:1;
00075         unsigned Broadcast:1;
00076         unsigned PacketDefer:1;
00077         unsigned ExcessiveDefer:1;
00078         unsigned MaximumCollisions:1;
00079         unsigned LateCollision:1;
00080         unsigned Giant:1;
00081         unsigned Underrun:1;
00082         WORD     BytesTransmittedOnWire;
00083         unsigned ControlFrame:1;
00084         unsigned PAUSEControlFrame:1;
00085         unsigned BackpressureApplied:1;
00086         unsigned VLANTaggedFrame:1;
00087         unsigned Zeros:4;
00088     } bits;
00089 } TXSTATUS;
00090 
00091 typedef union {
00092     BYTE v[4];
00093     struct {
00094         WORD     ByteCount;
00095         unsigned PreviouslyIgnored:1;
00096         unsigned RXDCPreviouslySeen:1;
00097         unsigned CarrierPreviouslySeen:1;
00098         unsigned CodeViolation:1;
00099         unsigned CRCError:1;
00100         unsigned LengthCheckError:1;
00101         unsigned LengthOutOfRange:1;
00102         unsigned ReceiveOk:1;
00103         unsigned Multicast:1;
00104         unsigned Broadcast:1;
00105         unsigned DribbleNibble:1;
00106         unsigned ControlFrame:1;
00107         unsigned PauseControlFrame:1;
00108         unsigned UnsupportedOpcode:1;
00109         unsigned VLANType:1;
00110         unsigned Zero:1;
00111     } bits;
00112 } RXSTATUS;
00113 
00114 
00115 
00116 /******************************************************************************
00117 * PHY Register Locations
00118 ******************************************************************************/
00119 #define PHCON1  0x00
00120 #define PHSTAT1 0x01
00121 #define PHCON2  0x10
00122 #define PHSTAT2 0x11
00123 #define PHIE    0x12
00124 #define PHIR    0x13
00125 #define PHLCON  0x14
00126 
00127 
00128 typedef union {
00129     WORD Val;
00130     WORD_VAL VAL;
00131 
00132     // PHCON1 bits ----------
00133     struct {
00134         unsigned :8;
00135         unsigned PDPXMD:1;
00136         unsigned :7;
00137     } PHCON1bits;
00138 
00139     // PHSTAT1 bits --------
00140     struct {
00141         unsigned :2;
00142         unsigned LLSTAT:1;
00143         unsigned :5;
00144         unsigned :8;
00145     } PHSTAT1bits;
00146 
00147     // PHCON2 bits ----------
00148     struct {
00149         unsigned :4;
00150         unsigned RXAPDIS:1;
00151         unsigned :3;
00152         unsigned HDLDIS:1;
00153         unsigned :5;
00154         unsigned FRCLNK:1;
00155         unsigned :1;
00156     } PHCON2bits;
00157 
00158     // PHSTAT2 bits --------
00159     struct {
00160         unsigned :8;
00161         unsigned :2;
00162         unsigned LSTAT:1;
00163         unsigned COLSTAT:1;
00164         unsigned RXSTAT:1;
00165         unsigned TXSTAT:1;
00166         unsigned :2;
00167     } PHSTAT2bits;
00168 
00169     // PHIE bits -----------
00170     struct {
00171         unsigned :1;
00172         unsigned PGEIE:1;
00173         unsigned :2;
00174         unsigned PLNKIE:1;
00175         unsigned :3;
00176         unsigned :8;
00177     } PHIEbits;
00178 
00179     // PHIR bits -----------
00180     struct {
00181         unsigned :2;
00182         unsigned PGIF:1;
00183         unsigned :1;
00184         unsigned PLNKIF:1;
00185         unsigned :3;
00186         unsigned :8;
00187     } PHIRbits;
00188 
00189     // PHLCON bits -------
00190     struct {
00191         unsigned :1;
00192         unsigned STRCH:1;
00193         unsigned LFRQ0:1;
00194         unsigned LFRQ1:1;
00195         unsigned LBCFG0:1;
00196         unsigned LBCFG1:1;
00197         unsigned LBCFG2:1;
00198         unsigned LBCFG3:1;
00199         unsigned LACFG0:1;
00200         unsigned LACFG1:1;
00201         unsigned LACFG2:1;
00202         unsigned LACFG3:1;
00203         unsigned :4;
00204     } PHLCONbits;
00205     struct {
00206         unsigned :1;
00207         unsigned STRCH:1;
00208         unsigned LFRQ:2;
00209         unsigned LBCFG:4;
00210         unsigned LACFG:4;
00211         unsigned :4;
00212     } PHLCONbits2;
00213 } PHYREG;
00214 
00215 
00216 /******************************************************************************
00217 * Individual Register Bits
00218 ******************************************************************************/
00219 // ETH/MAC/MII bits
00220 
00221 // EIE bits ----------
00222 #define EIE_PKTIE       (1<<6)
00223 #define EIE_DMAIE       (1<<5)
00224 #define EIE_LINKIE      (1<<4)
00225 #define EIE_TXIE        (1<<3)
00226 #define EIE_TXERIE      (1<<1)
00227 #define EIE_RXERIE      (1)
00228 
00229 // EIR bits ----------
00230 #define EIR_PKTIF       (1<<6)
00231 #define EIR_DMAIF       (1<<5)
00232 #define EIR_LINKIF      (1<<4)
00233 #define EIR_TXIF        (1<<3)
00234 #define EIR_TXERIF      (1<<1)
00235 #define EIR_RXERIF      (1)
00236     
00237 // ESTAT bits ---------
00238 #define ESTAT_BUFER     (1<<6)
00239 #define ESTAT_RXBUSY    (1<<2)
00240 #define ESTAT_TXABRT    (1<<1)
00241 #define ESTAT_PHYRDY    (1)
00242     
00243 // ECON2 bits --------
00244 #define ECON2_AUTOINC   (1<<7)
00245 #define ECON2_PKTDEC    (1<<6)
00246 #define ECON2_ETHEN     (1<<5)
00247     
00248 // ECON1 bits --------
00249 #define ECON1_TXRST     (1<<7)
00250 #define ECON1_RXRST     (1<<6)
00251 #define ECON1_DMAST     (1<<5)
00252 #define ECON1_CSUMEN    (1<<4)
00253 #define ECON1_TXRTS     (1<<3)
00254 #define ECON1_RXEN      (1<<2)
00255     
00256 // ERXFCON bits ------
00257 #define ERXFCON_UCEN    (1<<7)
00258 #define ERXFCON_ANDOR   (1<<6)
00259 #define ERXFCON_CRCEN   (1<<5)
00260 #define ERXFCON_PMEN    (1<<4)
00261 #define ERXFCON_MPEN    (1<<3)
00262 #define ERXFCON_HTEN    (1<<2)
00263 #define ERXFCON_MCEN    (1<<1)
00264 #define ERXFCON_BCEN    (1)
00265     
00266 // MACON1 bits --------
00267 #define MACON1_TXPAUS   (1<<3)
00268 #define MACON1_RXPAUS   (1<<2)
00269 #define MACON1_PASSALL  (1<<1)
00270 #define MACON1_MARXEN   (1)
00271     
00272 // MACON3 bits --------
00273 #define MACON3_PADCFG2  (1<<7)
00274 #define MACON3_PADCFG1  (1<<6)
00275 #define MACON3_PADCFG0  (1<<5)
00276 #define MACON3_TXCRCEN  (1<<4)
00277 #define MACON3_PHDREN   (1<<3)
00278 #define MACON3_HFRMEN   (1<<2)
00279 #define MACON3_FRMLNEN  (1<<1)
00280 #define MACON3_FULDPX   (1)
00281     
00282 // MACON4 bits --------
00283 #define MACON4_DEFER    (1<<6)
00284     
00285 // MICMD bits ---------
00286 #define MICMD_MIISCAN   (1<<1)
00287 #define MICMD_MIIRD     (1)
00288 
00289 // MISTAT bits --------
00290 #define MISTAT_NVALID   (1<<2)
00291 #define MISTAT_SCAN     (1<<1)
00292 #define MISTAT_BUSY     (1)
00293     
00294 // EFLOCON bits -----
00295 #define EFLOCON_FCEN1   (1<<1)
00296 #define EFLOCON_FCEN0   (1)
00297 
00298 
00299 
00300 // PHY bits
00301 
00302 // PHCON1 bits ----------
00303 #define PHCON1_PDPXMD   (1ul<<8)
00304 
00305 // PHSTAT1 bits --------
00306 #define PHSTAT1_LLSTAT  (1ul<<2)
00307 
00308 // PHCON2 bits ----------
00309 #define PHCON2_FRCLNK   (1ul<<14)
00310 #define PHCON2_HDLDIS   (1ul<<8)
00311 #define PHCON2_RXAPDIS  (1ul<<4)
00312 
00313 // PHSTAT2 bits --------
00314 #define PHSTAT2_TXSTAT  (1ul<<13)
00315 #define PHSTAT2_RXSTAT  (1ul<<12)
00316 #define PHSTAT2_COLSTAT (1ul<<11)
00317 #define PHSTAT2_LSTAT   (1ul<<10)
00318 
00319 // PHIE bits -----------
00320 #define PHIE_PLNKIE     (1ul<<4)
00321 #define PHIE_PGEIE      (1ul<<1)
00322 
00323 // PHIR bits -----------
00324 #define PHIR_PLNKIF     (1ul<<4)
00325 #define PHIR_PGIF       (1ul<<2)
00326 
00327 // PHLCON bits -------
00328 #define PHLCON_LACFG3   (1ul<<11)
00329 #define PHLCON_LACFG2   (1ul<<10)
00330 #define PHLCON_LACFG1   (1ul<<9)
00331 #define PHLCON_LACFG0   (1ul<<8)
00332 #define PHLCON_LBCFG3   (1ul<<7)
00333 #define PHLCON_LBCFG2   (1ul<<6)
00334 #define PHLCON_LBCFG1   (1ul<<5)
00335 #define PHLCON_LBCFG0   (1ul<<4)
00336 #define PHLCON_LFRQ1    (1ul<<3)
00337 #define PHLCON_LFRQ0    (1ul<<2)
00338 #define PHLCON_STRCH    (1ul<<1)
00339 
00340 #endif